20151217

Solid State Technology

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In this month’s issue you'll find…
Variation in build-up substrate layer thicknesses and its impact on FCBGA BLR performance
By Jaimal Williamson, Texas Instruments, Dallas, TX
Subtleties in thicknesses between the alternating Cu metal and dielectric layers within a build-up substrate can impact BLR performance.
Advanced lithography and electroplating approach to form high-aspect ratio copper pillars
By Keith Best, Rudolph Technologies, Wilmington, MA and Phillip Holmes, TEL NEXX, Billerica, MA
It is possible to fabricate copper pillars more than 100µm in height, with aspect ratios up to 6:1, using advanced packaging stepper lithography in conjunction with electroplating.
Practical limits for metallization scaling in fabs
By Ed Korczynski, Senior Technical Editor
Beyond economic limits due to litho limitations, the inherent need for a physical barrier an electrical limit on the ability to scale.
Feed-forward overlay control in lithography processes using CGS
By Doug Anberg and David M. Owen, Ultratech, San Jose, CA
Feed-forward can be applied for controlling overlay error by using Coherent Gradient Sensing (CGS) data to reveal correlations between displacement variation and overlay variation.
The Most Expensive Defect; Part 2
By David W. Price and Douglas G. Sutherland, KLA-Tencor, Milpitas, CA
Because yield and reliability defects stem from the same source, reducing the source of yield defects will have the side benefit of also reducing reliability defects. Increasing process steps and the tyranny of numbers.
When front-end-of-line and back-end-of-line reliability meet
Due to the further scaling and increasing complexity of transistors, the boundaries between back-end-of-line and front-end-of-line reliability research are gradually fading. Imec's team leaders Kristof Croes and Dimitri Linten give their vision on the future of reliability research.
Regards,

Pete Singer
Editor-in-Chief

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